1. Field of the Invention
The solution according to one or more embodiments of the present invention relates to the electronics field. More specifically, such a solution relates to non-volatile memory devices.
2. Discussion of the Related Art
Non-volatile memory devices are used in whatever application that requires the storage of binary digits (or bits) of information that should be held even when the memory devices are not powered.
An example of such devices is represented by flash memory devices being integrated in chips of semiconductor material. In general, each flash memory device includes a plurality of sectors of electrically erasable and programmable memory cells; each sector is formed in a respective electrically isolated well of the chip. Each memory cell typically includes an N-channel MOS transistor with a floating gate structure; such transistor has a drain terminal, a source terminal and a gate terminal, in a completely similar manner to a standard MOS transistor, with the addition of a further floating gate region that is buried within an oxide layer so as to be electrically isolated.
The information bit is physically stored within each memory cell in the form of electrical charge within the floating gate, which defines a corresponding threshold voltage of the transistor; in particular, the memory cell is erased at a low threshold voltage (floating gate being free from electric charges) and programmed at a high threshold voltage (electrical charges being trapped in the floating gate). As is known, in flash memory devices, the programming can be performed on individually selected memory cells, whereas the erasing can be performed only for whole selected sectors (even concurrently on more of them). In particular, for erasing a selected sector, a very high voltage difference is applied between the well thereof and the control terminals of the respective memory cells; this is typically performed by biasing the well to a very high positive voltage (e.g., 8V) and the control terminals to a negative voltage being very high in absolute value (e.g., −8V).
Although flash memory devices offer high performance in terms of speed and functionality, they still have drawbacks that, in high-performance applications (such as automotive applications), may even significantly limit reliability and robustness thereof.
In particular, after the erasing of selected sectors, the respective control terminals and wells should be properly de-biased (through positive and negative discharges, respectively) so as to enable their efficient re-biasing in subsequent operations. To such purpose, each sector of the flash memory device includes a respective dedicated discharge circuit (or sector discharger) for discharging the corresponding well; instead, the flash memory device includes a common discharge circuit (or central discharger) being shared by all the sectors of the flash memory device for selectively discharging the control terminals of all the memory cells of the selected sectors.
However, such de-biasing operation has criticalities due to parasitic couplings, which generally can be modelled as an equivalent capacitive coupling between the control terminals of the memory cells of each sector and the respective well; in particular, such parasitic couplings may include parasitic diodes at the interface of diffusions having different doping (e.g., between the P-doped well and N-doped diffusions) and parasitic capacitors between conductive elements (e.g., between the control terminal and the source terminal of each memory cell).
Moreover, since the control terminals of the memory cells of all the selected sectors are concurrently connected to the central discharger, the latter is coupled (through a total capacitive coupling given by the sum of all the equivalent capacitive couplings of each selected sector) to the sector dischargers of the selected sectors, which affect the respective discharges during the de-biasing operation. In addition, since such total capacitive coupling depends on a number (being variable from time to time) of selected sectors, the discharge of the control terminals (being performed by the central discharger) and that of the wells (being performed by the respective sector dischargers) will have a trend being unpredictable a priori and variable from time to time.
In particular, such total capacitive coupling in some cases may involve spurious voltage glitches on the control terminals with even very high values (e.g., −10V) and not negligible durations; this causes a substantial impossibility to ensure a full functionality of the flash memory device, since such spurious voltage glitches, causing dangerous electrical stresses, may involve a degradation in performance and reliability of the flash memory device, or even its breakage in relatively short times.